STUDENT TEXT ABR30533-1

PREPARE ; THE MAN

Computer Systems Department

OUTPUT SYSTEM C697-416L-ST

24 April 1967

Keesler Technical Training Center Keesler Air Force Base, Mississippi

Designed For ATC Course Use

Computer Systems Department Student Text KTTC, Mississippi ABR30533-1 24 April 1967

OUTPUT SYSTEM

This Student Text provides student study material in support of Course

ABR30533-1, CONTENTS CHAPTER TITLE PAGE 1 Introduction to Outputs 1 2 Output Control Element, Detailed Analysis 60 3 Output Storage Element, Detailed Analysis 125 4 Test Equipment Section 245

5 AN/FSQ-8 Output System 281

CHAPTER1. INTRODUCTION TO OUTPUTS 1. Function of Output System in AN/FSQ-7 Combat Direction Central

The Output System in the AN/FSQ-7 Combat Direction Central transfers output messages from the Central to adjacent Centrals and remote sites through telephone facilities. (See Figure 1-1.) After forming an output message, the Central Computer System stores it on the output buffer (OB) fields of the LOG drum in the Drum System for eventual transfer to the Output System. The Output System accepts the output message from the OB fields and transfers the message to telephone facilities for transmission to its intended destination(s). The path followed by the output message from the Central Computer System to the telephone facilities is shown in Figure 1-2. The general manner in which the Output System accepts output messages from the OB fields and transfers them to telephone facilities is discussed below. Because the Output System is logically divided into two elements, the output control element and the output storage element, as shown in Figure 1-3, the following general description of the operations performed by the Output System is treated by referring to these two elements.

2. Output Control Element

The output control element primarily controls the flow of output message words from the OB fields of the LOG drum to the output storage element. Another function of the output control element is to make available to the Central Computer System specific data which is used by the Air Defense program as an aid in controlling the transmission time of output messages. The output control element also provides visual indications of alarm conditions that might occur in the Output System and, in addition, contains Output System test equipment which can be used both as an aid in detecting the sources of trouble within the Output System and as an aid in checking certain elements of the Input System.

3. Output Storage Element

The output storage element temporarily stores the words of an Output message and then, at the completion of read-in (whenthe complete message is present in the output storage element) transfers the message serially to telephone terminal equipment. This element contains three storage sections; each accommodates a different class of output messages. Output messages are grouped into three classes: ground-to-air time division (G/A-TD), ground-to-ground (G/G), and teletype (TTY). The storage sections are labeled accordingly, the G/G storage section, the G/A-TD storage section, and the TTY storage section. These storage sections receive and store output messages and then transfer them serially to the telephone terminal equipment. However, the transfer rate employed by the storage sections differs and depends upon the class of output message handled. Output messages in the G/G and G/A-TD classes are sent over telephone data channels to sites equipped with automatic input equipment. Sites not equipped with automatic input devices are supplied with teletypewriter receivers. Output messages destined for such sites are in the TTY message class and are transferred by the TTY storage section to telephone equipment at the standard TTY rate of 60 words per minute (wpm).

aes TELEPHONE

DATA “LINK DATA CIRCUIT TRANSMITTERS

| a | AN/FSQ-7 = CIRCUIT T

OuUTPU COMBAT DIRECTION SYSTEM

| TELEPHONE ADJACENT OATA CIRCUIT CENTRALS

TELEPHONE RADAR

| DATA CIRCUIT SITES

Figure 1-1. Remote Sites, Block Diagram

CENTRAL COMPUTER SYST

Figure 1-2. Output Message Flow, Block Diagram

Output Messages

1. General

An output message is a communication sent from an AN/FSQ-7 Combat Direction Central to adjacent Centrals or remote units. The Central Computer System performs various operations, controlled by the air defense situation data supplied to the Central Computer System by radar sites adjacent Centrals, and by personnel (manually) through the Input System. If the results of these operations are to be transmitted to remote units, such results are formed into output messages. As previously indicated, an output message falls into one of three classes: G/G, G/A-TD, and TTY. The data used to form each message class and the purpose or purposes of each class are described below.

Ground-to-air TD messages are composed of data which will help manned fighter aircraft intercept assigned enemy targets. The G/A-TD messages are transmitted

‘CENTRAL COMPUTER SYSTEM

OUTPUT TRANSMISSION ALARM TIME DATA

cae OUTPUT [ouTPUT STORAGE ELEMENT

CONTROL ae ELEMENT

| 6/6 G/G DATA reece enone | | P G/A-TD GROUND-TO-AIR * | G/A-TO ree DATA TIME DIVISION EQUIPMENT TTY TTY DATA TELETYPE

% NOT USED IN AN/FSQ-86

Qa aa oe a=

Figure 1-3. Output System, Block Diagram

from the Central to the remote G/A-TD data-link transmitters which provide the radio link with the aircraft.

A G/G message is composed of either crosstelling (XTL) data, forwardtelling data, height-finder request, or a missile control message. Ground-to-ground XTL messages are transmitted to adjacent AN/FSQ-7 Combat Direction Centrals, and G/G forwardtelling messages are sent to an AN/FSQ-8 Combat Control Central. Crosstelling information is data that aids the receiving Central in performing its assigned function. Forwardtelling data is ‘a report on the over-all situation in the area of the sending Central. Another type of G/G message is composed of a height-finder request which is sent to height-finding equipment at a radar site.

A height-finder request message is employed whenever the altitude of a specific target is required. The remaining type of G/G message is used for in-flight control of unmanned interceptors (missile).

Teletype messages are formed of either information intended for higher head- quarters, information for non-automatic adjacent sectors (sectors not equipped with AN/ FSQ-7 Combat Direction Centrals), or early warning information intended for anti- aircraft batteries. Forward-telling information sent to higher headquarters is a summary tabulation of the up-to-the-minute air defense situation. The TTY messages sent to non-automatic adjacent sectors contain information similar to the data in G/G messages. Teletype messages sent to the anti-aircraft batteries are composed of early warning radar data.

2. Timing of Output Message Transmissions

The time for the transmission of each output message is selected in the Central Computer System, and certain Output System Circuits ensure that the message is trans- mitted at the selected time. The reasons for this control and the means by which it is accomplished are described in the following text.

Output messages must be transmitted in correct sequence within each of the three classes: G/G, G/A-TD, and TTY. In addition, certain types of messages in each class must be transmitted at the proper times.

3. Message Formation. (Refer to Table 1-1.)

a. General

An output message as formed by the Central Computer System is composed of several words; the exact number of words used to form each message varies with the class of the message. A G/G message contains five words; a G/A-TD message, four words; and a TTY message, an indefinite number of words. Each drum word is composed of 32 bits and is divided into halves, the left half-word and the right half-word. The right half-word contains output data to be transmitted, and the left half-word is made up of address data and a burst number. After formation, and prior to storing the word on the OB fields for eventual transfer to the Output System, a parity bit is added, in- creasing the total number of bits to 33.

b. Left Half-Word

The left half-word of each word contains a 3-bit section address (LS-L2), a o-bit register address -L7) and a burst number which may contain as many as

eight bits (L8- . This data is used to inform the Output System of the output storage section that is to transmit the right half-word, the storage register in the selected output storage section where the right half-word is to be stored, and the burst period during which the right half-word is to be accepted from the OB fields and transmitted by the selected storage section. The combination of the section address and register address determines the group of remote sites to which the right half-word is transmitted. In

O Q Ls L2b3 L7| 18 Li5{ «RS 123456789 1011 R15 s jog, P zy OSA] ORA | BurstGount Z,,-24c1 Information / br o~ ! Sug? 5 2 00000000 XTELL to an AN/FSQ-7 »D \ wg r¢8 11111111 Forward Tell to an AN/FSQ-8 D> Fi 4 g 0 377, Height Finder Request (typical format) - ef 256, , cts Old Height Reg # Radar Site Adr (Word #0) 00 Y Coordinates---- 0000 #1 | 00 xX Coordinates---- 0000 #2 Ctr stepped 00 Spare Special Request 0000 #3 oS every 92/1300 sec 00 000000000000000000000000 0000 #4 Approx 70.7 msec Missile Control & Missile Master (Nike) fee) Reset every 18 sec v phere fares wie Information

| Loe £ O11 } | 00000 00000000 1 | Command / Command / Command 11000, 00011111, A Gry 0+30, | 0-37, L a 2540 32, 0 cts WwW / a. 0 24,0 Ctr stepped A / Ne PT a | Regs every 45/91 sec Y Approx 1/2 sec S

| Lada 7 mone | 25, 9 Slot 45 phone nee eis Me ocLt' Reset Approx every 16 secs Kh | ey

ent Each slot is associated with an individual phone line.

OUTPUT DRUM WORD LAYOUTS

Table 1-1

Dp WAS EVEN PH

On pu qal wees 2 z Sw —_ “~~ e LS L4L3 L7 L8 L15 ORA Burst Geunt ZZ, 4-.

00000000 11111111

0-377, 256 cts

2

Stepped every 90 msec

23.04 sec Reset

L7? L8 Burst-@oanat 7,,,

hh,

“101 | | 00000 0000000 / | 01011 1111111 2 2 / } 9-913 0-177

co

128 7 a ee

Stepped every

180 msec

-Xmitter Site

RS 12%456789 1011 ----

Information

Aircraft Address Spare

Xmitter Site Msg Label

Command A

Command B

Command C Command D

PS 123456789 10 11 ----

Information

Aircraft Address Spare

Msg Label

Command A Command B

Command C Command D

In G/A-TD, Dual Channel, each slot is associated with two phone lines.

In G/A-TD, Single Channel, all information is transmitted over one phone line.

OUTPUT SYSTEM DRUM WORD LAYOUTS

Table 1-2

2 Message 3

2 Message 3

order to understand how the section and register addresses are used to accomplish this, a short discussion pertaining to the logical composition of the storage device employed in the output storage sections and to the telephone facility connections is required.

The output storage sections employ ferrite core arrays as storage devices. An array is composed of 26 core registers, each of which has the capacity to store a right half-word. An array within an output storage section is logically divided into slots, each formed by the number of registers required to accommodate the right half-words of one output message. Therefore, a slot can store one output message. Since the number of words forming an output message varies according to the output message class, the number of registers forming a slot differs in each output storage section. A G/G slot is composed of five registers; a G/A-TD slot, of four registers; and a TTY slot, of only one register. The TTY slot requires only one register because only one word of a teletype message is transmitted during a teletype burst period.

During the formation of an output message, the remote site intended to re- ceive this message is known as a result of the Central Computer System operations performed on air defense situation data. A binary code for a storage section is selected and assigned as a section address. This section address is assigned to each left half- word of the output message. The section address is a general address because it merely specifies the output storage section that is to transmit the message. In order to complete the addressing of the output message, the* ‘words: ‘of the message must be addressed to those registers composing the slot in the selécted output storage section array that supplies the telephone circuit connected to the intended destination of the message. Therefore, successive words in the output message are sequentially assigned the register addresses of the registers in the slot concerned.

The remaining portion of, a left half-word is the burst number. The burst number that is assigned to a message indicates the burst period during which the words of the message are to be accepted by the Output System from the OB fields and then transmitted. The same burst number is assigned to each left half-word of the message (or messages, if there is more than one in a burst).

% . he: pie de RS ‘ose’, 7 4 yf Deva Oat eR en De HOC ES a ae tek “te amd wk wets bh ge Leg Sep RES ae hs

7 “ew a . ; Pees ca OF capsae . fe

a Fy a es wh ta Be get he Ae Se Ee! Ue : ,,

c. Right Half-Word

The right half-word of each output message word is formed by the Central Computer System, using only a part of the data composing a complete output message. The remaining output message data is used to form the right halves of the other words in the message.

A G/G message contains five right-half drum words (a total of 80 bits employed by the Central to carry either XTL information to an adjacent Central, forward- telling data to an AN/FSQ-8 Combat Control Central, or a height-finder request to a radar site. The data used to form a G/G XTL or forwardtelling message can be varied by the air defense program in the Central Computer System. Therefore, the amount of XTL or forwardtelling data used to form each right half-word of a G/G message is not fixed.

oN ut eaten

Each right half-word of a typical XTL or forwardtelling message is formed by the Central Computer System. The last (third) type of G/G message is employed to carry height-finder requests to radar sites.

A G/A-TD message is composed of four right half-words that are separated into groups of two right half-words and transmitted over separate telephone channels to manned interceptors via data-link transmitters. Two data phone lines are used to transmit the G/A-TD message to the manned interceptor. One data phone line handles information relating to site address, aircraft address, and the message label, whereas the command data associated with the G/A-TD message is transmitted over the other data phone line.

One G/A-TD message contains four commands. The G/A-TD messages are sent from the Central via data-link transmitters that are located within a given area, with each transmitter operating on the same assignedfrequency. Selection of a particular data-link transmitter is established by the site address portion of the G/A-TD message. If a G/A-TD message is addressed to a particular aircraft in a group of aircraft, only that aircraft will take action on the transmitted message.

A TTY message is employed by the Central to carry information to remote sites not equipped with automatic input devices through telephone TTY circuits. Each right half-word of a TTY message contains the binary equivalent of three TTY code symbols. A TTY code symbol represents either a letter, a figure, or a TTY operation. Table 1-3 shows the TTY letter, figure, or operation associated with a 5-bit binary code symbol. As shown in Table 1-3, a binary code may represent either a letter or a figure. Because of this, a code symbol representing either of the TTY operations, entitled letters or figures, must be transmitted prior to the group of letter or figure codes. The three 5-bit code symbols employed to form a right half-word of a TTY message depend upon the data to be transmitted. The 15 bits of the three 5-bit code symbols occupy bit positions R1 through R15 of a TTY right drum word. Bit RS is always al.

d. Parity Bit

A parity bit is added to the drum word to cause the sum of the 1’s in a word to be odd if odd parity is desired and to be even if even parity is desired.

A parity check for the correctness of the drum word is accomplished by counting the number of 1 bits of the drum word which are stored in the OB register and affecting odd parity.

In the Central Computer System, after the left and right halves of a word are formed, a count is made of the 1 bits in the word. When an odd total is discovered, a 0 parity bit is assigned; however, should an even total result, a 1 parity bit is added. In both cases, the total number of 1 bits in the word plus the parity bit is odd. There- fore, the number of 1 bits in a word, together with its parity bit, when placed on the OB fields, should always be odd. The 32-bit word plus the parity bit is referred to as a 33-bit drum word. When the Output System reads a drum word from the OB fields, it performs a parity count to determine whether or not the word is acceptable. The word is accepted if it has odd parity and rejected if it has even parity.

LETTERS FIGURES CODE SIGNALS

00111 01100 10001 01101 01111] 01001 10100 11010 10011 00101 00001 10110 11000 11001 11100 10010 00010 10101 ell 01011 11110 00011 10000 . 00110 01000 01010 01110

Space 11011 Ae e Carriage Return 11101 ys Line Feed sep 10111 er")

Figures 00100 19ck

SRP Lot K

~~

=v om -— © = go -—- WH’?

NUD hr OW

NX ES GHNDOVOSZSZSrASC"LOANHBOVADS or™ NWN -~:

Letters 00000

Blank lll

Table 1-3. Teletype Code Characters

Drum Storage 1. General

Note: For a detailed discussion of the LOG Drum and the three OB fields refer to the Job Proficiency Guide of the C.C. Drum System.

There are three OB fields on the LOG drum in the Drum System upon which drum words are stored by the Central Computer System for eventual transfer to the Output System. These OB fields are used consecutively and therefore may be thought of as one triple-size drum field. One restriction upon this concept is the fact that a con- tinued reading from, and writing onto, these fields is interrupted because a delay of 120 usec is introduced when switching from one field to the next. These OB fields are divided into 6,144 registers (2,048 per field); however, only 2,036 registers per field are used to store drum words because 120 usec are required at the beginning of each field to allow for switching fields. Thus, 12 drum registers per field have no usable information in them (dead registers); consequently, only 2,036 drum-word registers are used. The drum rotation is such that successive registers are spaced 10 usec apart.

The drum words of an output message are written onto the OB fields at the maximum rate of 50,000 drum words per second. They remain on the OB fields until the arrival of the burst period, during which the output message is intended for trans- mittal by the Output System. At the start of this burst period, the drum words of the output message are accepted by the Output System from the OB fields at the maximum rate of 100,000 drum words per second, but not for the same section.

In addition to transferring drum words stored on the OB fields to the Output System, the Drum System supplies the Output System with OD LOG drum timing pulses. The Output System utilizes these timing pulses to synchronize its operations with those of the Drum System.

2. OB Fields Writing

The drum words of an output message are written on either all odd or all even drum-word registers of the OB fields, as specified by the Central Computer System. Since there is a 10-usec interval between successive registers, the minimum interval between the writing of successive drum words of an output message on the OB fields is 20 usec; i.e., writing cannot occur at a rate greater than 50,000 drum words per second. The drum words of the same output message are intended for a specific storage section of the Output System, which receives them at the same rate at which they are written onto the OB fields. The maximum rate at which information can be placed in a ferrite core array employed by an output storage section is 50,000 pulses per second (pps). Thus, limiting the writing of successive drum words onto only odd or even drum regis- ters ensures that the rate at which the drum words of a message are transferred to a particular core array never exceeds 50,000 drum words per second.

Successive drum words of one message are not necessarily written onto these

drum fields in successive odd or even registers. Instead, each drum word is written onto the first odd or even drum-word register that is available to the drum word.

10

A drum-word register is considered to be available if its contents have been accepted by the Output System; it is considered unavailable when it stores a drum word that has not yet been accepted by the Output System. Thus, when a drum word is accepted by the Output System, the status of its associated drum-word register is changed to indicate an available register. In like manner, the:status of a register is changed to unavailable when a drum word is writtenontothe register. No separate erasing procedure is performed when a drum word is accepted by the Output System because the action of writing a new drum word onto an available register effectively erases the old drum word as part of the write-in process.

Frequently, each successive drum word must wait for a register to become available; consequently, successive drum words are often placedon the OB fields several drum-word registers apart. Therefore, the interval between the writing of successive drum words of the same message may be greater than 20 usec (but the interval is always a multiple of 20 usec).

3. OB Fields Reading

The contents of the drum-word registers on the OB fields are read consecu- tively and transferred to the Output System. Since there is a 10-usec interval between drum-word registers, the drum words cannot be read ata rate greater than 100,000 drum words per second. Each drum word received by the Output System is examined and either accepted, rejected for being in error, or rejected for arriving too soon. The statuses of the registers associated with the drum words that are either accepted or rejected for being in error are changed to available. The drum words that are rejected for arriving too soon remain on the OB fields. These rejected drum words contain good information and will be accepted at a later time. Consequently, the statuses of the registers containing the rejected drum words remain unchanged to prevent the writing of new drum words over still useful information.

4. Log Drum OD Timing Pulses

The LOG drum OD timing pulses are usedto synchronize the transfer operations of the Drum System with the processing operations of the Output System. There are four OD timing pulses, designated OD 1, OD 2, OD 3, and OD 4. These pulses occur in sequence from OD 1 through OD 4 with a spacing of 2.5 usec between successive pulses. Therefore, an OD cycle, which is the interval between an OD 1 pulse and a following OD 1 pulse, is 10 usec. The OD pulses are generated continuously, with every OD 4 pulse followed 2.5 usec later by an OD 1 pulse.

Ferrite Core Storage Note: Refer to Figure 1-4.

1. The ferrite core array is a coincident-current storage device, similar in some ‘respects to the core memory of the Central Computer System. This array consists of 572 ferrite cores arranged to form 22 columns and 26 rows. As shown in Figure 1-4, the two axes are termed the message axis and the address axis, and each row is known as an addresss register.

11

DRESS AXIS

MESSAGE AXIS 22 Columns

FERRITE

Figure 1-4

MESSAGE AXIS

Half - Write Current

Half - Write

Current

Figure 1-5

The ferrite core is a device with square loop hysteresis characteristics, capable of two saturated states. These two states represent binary digits 0 and 1. Read-in of information switches one or more cores in the array from the 0 state to the 1 state and allows other cores to remain in the 0 state. Readout of information sequentially senses the state of all cores in the array and switches the cores previously set to the 1 state back to the 0 state.

During read-in of information, a particular core in the array is set to the 1 state upon receipt of two half-write currents: one from the address axis and one from the message axis. Each column and each row is provided with a 2-turn read-in winding which carries the half-write current. Figure 1-5 shows a simplified version of an array and the method by which a particular core is selected for read-in of information. The coincidence of two half-write currents applied to a particular core results in the full-write current necessary to switch the core from the saturated 0 state to the saturated 1 state. Note: Refer to Figure 1-5.

Readout of information from an array necessitates two windings for each column and each row in addition to the read-in windings previously mentioned. (See Figure 1-6.) These windings are termed the readout winding and the sense winding. Readout differs from read-in in that it is not produced by two coincident currents; instead, a single readout current flows through the 2-turn readout winding of all ferrite cores of a column. Sequentially, one column after another is read out in this manner. This process is illustrated in Figure 1-7.

When the readout current pulse is applied to a given column, all cores in that column that were previously switched to a 1 state are switched back to the 0 state. The sense winding is a single-turn winding which connects all the cores in a given row. The effect of pulsing the readout winding is to induce a voltage in the sense winding. The induced voltage is of either of two configurations, depending upon whether the core was already in a 0 state or whether the core switched from the 1 state to the 0 state. Refer to Figure 1-7.

In accomplishing the read-in and readout processes in accordance with require- ments imposed on the Output Storage System, various special circuits are employed. These circuits are explained in detail in Chapter 3. The paragraphs which follow explain the over-all relationships of these circuits with each other and with the ferrite core array.

2. Array Read-In Note: Refer to Figure 1-8.

The ferrite cores of each column and each row of an array receive half-write current from a tape core device known as a core current driver (CCD). (See Figure 1-8.) The CCD is switched from either of two saturated states, 0 and 1. A core is said to be set when it is switched to the 1 state and reset when it is switched to the 0 state. A separate CCD is coupled to each row and each column of the array. When a CCD is switched from the 0 to the 1 state, the associated ferrite cores remain unaffected. However, when the CCD is switched from the 1 state back to the 0 state, a half-write current is transferred to all the ferrite cores in the associated row or column.

13

14

HALF -WRITE CURRENT

HALF ~ SENSE WINDING

WRITE | = ala MA Ds: ee

BN

READ- OUT PULSE

Figure 1-6. Core Windings, Simplified Diagram

REAO-OUT

INFORMATION

FROM SENSE WINDING

REAO-OUT PULSE

Figure 1-7. Readout by Columns, Simplified Diagram

08 REY

\n FO™ Wii tvrr ey eyed eee oe oe SET ORIVERS (STO) OUOOODUCOOOUOOOOOUUOOO > a AUVTUSRUSRUSRNSTENTNNT Pp 1% yy ovens ee OOOO DOOOOODOOOOROoOoOOO DRIVER (Rio) Lp ' | |

eee 0-9 OF a A 8 8S ce me 9 OS coe PU) Sa ae - 2 O—* OF oe m@ Q (soos tt . va ae" > oh BENT SASRAES DSS ASSe Eee Q 26-6 Go nee eed eA CRG a SSDS . OOS Ce ee ae —* Des 0 8 3 wae oe we Pesan | O—* 0 aaaaesaeet; pessesnes nina" Qasseeeesesithnsesseas ae amt 5 oa 8 8 SOA GO OU wa ww MNS TO OS CO 79 OS Oe 0 OS Co 8 OS ee tO OS eee Oo ONS CO = 8 OS Co ooo

0" OS 20 ON CO oo

=O" 8 Se ee

Bs A 2X

RESET- INHIBIT ORIVER (RID)

Figure 1-8. Ferrite Core Array with Associated Special Circuit Used for Read-In, Block Diagram

=3

~c= me »

15

The CCD is set to the 1 state by a circuit known as the set driver (STD). Particular STD’s are selected along the address and message axes. Pulsing the selected STD’s sets the associated CCD’s to the 1 state. The CCD’s must now be reset in order to transfer half-write currents into the array.

Associated with each ferrite core array are three identical circuits called reset-inhibit drivers (RID). Each RID is used to reset 16 CCD’s, the three RID’s simul- taneously switching all 48 CCD’s. When the RID’s are pulsed, all previously set CCD’s are reset to the 0 state, causing the read-in of half-write currents into the ferrite cores.

The RID’s also perform another function. Information is simultaneously trans- mitted to all arrays used in the Output System. However, information at a given time is intended for storage in only one array. To prevent entry of information into certain arrays, the RID’s associated with these arrays are pulsed in such a way as to reset all associated CCD’s. This inhibiting pulse, deliverei at the same time the STD’s are pulsed, cancels the effect of the set pulse delivered to the CCD’s. For that array in- tended for storing information, the RID does not inhibit the effect of the STD on the CCD.

To summarize the read-in operation: the RID’s are used to select the array intended for storing information by inhibiting the setting of CCD’s in all other arrays. The selected STD’s are pulsed, setting their associated CCD’s along the address and message axes of the selected array. Then the RID delivers a reset pulse to the CCD, resetting previously set 1’s to 0’s. Resetting of the CCD’s results in half-write currents being transferred to the associated ferrite cores in the row or column, Upon receipt of two coincident half-write currents, a ferrite core is switched from the 0 state to the 1 state. At the completion of the read-in operation, each selected address register of the array contains word information.

3. Array Readout

The current necessary to read out the ferrite cores in the array is produced by a thyratron core driver (TCD), a circuit which delivers a current output only when triggered. (See Figure 1-9.) One such driving circuit is associated with each column of the array.

Upon receipt of a pulse from a given TCD, all ferrite cores in the corresponding column which were previously switched to the 1 state are switched back to the 0 state.

Triggering of the TCD’s is controlled by core shift (CS) units, each unit con- trolling a separate driver. Each CS contains atape core which may be saturated in either of two states. This group of CS’s is known as the readout shift register.

In order to trigger the TCD’s sequentially, one at a time, the CS’s of the register must be sequentially switched, one at a time. This process is as follows: The core prime (CP), a driver circuit, pulses the first CS of the register, switching this core from the 0 to the 1 state. Then, all CS’s are pulsed simultaneously by the core shift driver (CSD). This latter pulse switches the first core back to 0. The switching causes two things: It switches the second CS from Oto 1, and it triggers the corresponding TCD which reads out the associated column (switches the ferrite cores to 0). The

16

Sg x “a

a b=

——wr?

FROM LAST CORE SHIFT

—> [} —> []} —+» []} —_> [] —» [] —e [] —> [] —> [ ] —» [] —+r [] —e [}

bala

OOO0UOO0ROO0O00000—

SOSRRERenanaa

FLUX AMPLIFIERS

[|

THYRATRON

CORE SHIFTS (CS) OF OU" FUT

HETEETTHETET ETH

OOOOUOOOOOOODOOUOOOOOOOO

CORE ORIVERS (TCO) ——e

& 38

Cs y SHIFT REGISTER

439

PEPE Pett tty

O—OO0O0OO00000 0OOOO0O00OG00000

I

CORE SHIFTS (CS)

<a— OF READ-OUT

CORE —o

PRIME

237

SHIFT REGISTER

e

24

CORE SHIFT ORIVER (CSO) ———e

Figure 1-9. Ferrite Core Array with Associated Special Circuits

Used for Readout, Block Diagram

17

CSD is then pulsed again, which switches the second CS back to 0 and the third CS to 1. Switching of the second CS to 0 fires the second TCD, which reads out the second column. This action continues until all columns have been read out. Thus, it might be said that readout information is serially entered into the readout shift register and that message information ig, taken from the column by parallel readout.

As each column of the array is pulsed, a voltage is induced into the sense winding of each row. Each sense winding drives a flux amplifier (FA). The FA either rejects the sense winding signal if the corresponding ferrite core contained a 0 or accepts it if the core contained a 1. Each FA drives a separate CS of the output shift register (OSR). Ferrite cores that contained 1’s cause associated CS’s to be switched to the 1 state; ferrite cores that contained 0’s allow associated CS’s to remain in the 0 state.

Since the information contained in all the ferrite cores of a column is entered simultaneously into the OSR, the register is said to receive this information by parallel entry.

Once the information contained in a column is transferred to the OSR, the CSD associated with the register is then pulsed repeatedly. With each pulse, information contained in each CS is transferred to its succeeding CS. Output from the register is taken from the last CS. The CSD is pulsed until all information is serially read out of the register.

To summarize the readout operation: the first CS in the readout register is switched to the 1 state by a core prime. This is necessary to initiate the serial switch- ing which takes place in the register. As the CSD pulses the readout shift register, the first CS is reset to 0, the second CS is set to 1, and the first TCD is triggered to reset all ferrite cores in the first column to 0. Information contained in the first column is transferred through the flux amplifiers to the OSR. The associated CSD is pulsed repeatedly until all information is serially readout of the register, output information being taken from the last CS in the register.

After the first column has been read out, the CSD associated with the readout shift register is pulsed again. This initiates readout of the second column. This action continues until all columns in the array have been readout. Thus, the word information

contained in each row of the array is serially readout column by column, The array is now ready for read-in again,

Special Circuits Used in the Output System

1. Tuning Fork Oscillator a. Definition and Description

A tuning fork oscillator (TFO) is a non-logic circuit which generates con- tinuous sine waves.

Table 1-4 lists the three models of the TFO’s utilized in AN/FSQ-7 and -8 equipments. Each circuit is listed by logic symbol showing the characteristics which

18

LOGIC BLOCK MODEL SYMBOL CHARACTERISTICS

A TFO Generates sine wave at a frequency of either 512 or 364 cps, depending on application. Am- plitude: 45v peak-to-peak.

B pl FO Generates continuous sine wave of 1,300 cps with normal amplitude of 7 to 8v peak-to-peak. C cTFO Generates sine wave at a frequency of 1,300

cps or 1,600 cps, depending on tuning fork used. Amplitude: 1lv peak-to-peak.

Table 1-4. Tuning Fork Oscillators

REFERENCE

SYMBOL FUNCTION R1 V1 grid return R2 Plate load resistor for V1 R3 V2 plate load resistor R4 V2 cathode resistor R5 Part of feedback network (with C2) Cl Bypass capacitor C2 Part of feedback network (with R5)

Table 1-5. Tuning Fork Oscillator, Model B Function of Detail Parts

19

distinguish one model from the other. Since all three models operate identically, only model B is discussed in detail.

b. Principles of Operation

The model pi FO shown in schematic form in Figure 1-10, will be discussed

as a typical TFO circuit in the following discussion. Table 1-5 lists associated detail parts and their functions.

The pif? produces a continuous 1300 cps sine wave whose period is ex-

tremely stable and accurate. The output from the tuning fork is a 0.5v peak-to-peak Sine wave which is applied to the grid of V2. This signal is amplified and fed to V1. The output signal from V1 is a positive 3v feedback of proper phase and magnitude to maintain oscillation of the tuning fork.

+250V + 250V e e

R2 R3

1.6 MEG 150K C2 0.01 UF

e Cl ; | O97 UF

ve | MEG TRIODE AMPLIFIERS

DRIVE COIL WAVEFORM 3v P/P

{ TUNING FORK

! PICKUP COIL OUTPUT 04- 0.5v P/P AMPLIFIER

7-BV P/P

TUNING FORK 1.3 KC

R4 2K

Figure 1-10. Tuning Fork Oscillator Model B, Schematic Diagram

2. Schmitt Trigger, Model A a. Definition and Description The model A Schmitt trigger (AST) is a non-logic circuit which produces

a constant amplitude bilevel output and is capable of voltage level discrimination and reasonably fast switching. The logic block symbol for the Schmitt trigger is shown.

20

far

U

b. Principles of Operation

The AST is shown schematically in Figure 1-11. Table 1-6 lists associated detail parts and their functions. In its quiescent condition, the grid of V1A is considerably negative with respect to its cathode. With the application of a rising positive level on the grid of V1A, this tube starts conducting. As conduction increases in V1A, the current through R3 causes a decrease in voltage at the plate of this tube and a consequent pro- portional drop at the grid of V1B because of the action of voltage divider R5 and R7. As the grid voltage of V1B is lowered, this tube heads toward cutoff. Since there is less conduction through the cathode resistors, the cathode goes more negative, increasing the positive-going difference between the grid and cathode of V1A and thereby driving the tube further into conduction. This action continues in the direction of conduction in V1A and cutoff in V1B until V1A saturates. Any further positive movement of the left grid results only in an increase in grid current. As the voltage level on the left grid is now lowered, a point in reached at which the feedback divider moves the right grid to a point where some conduction starts, raising the cathode slightly. Since the left grid is held by the input voltage and the cathode is now moving positive-wise, V1A tends toward cutoff, further raising its plate and the grid of V1B. The circuit has now switched back to the original state.

+150V +150V ® O

Ov = SS aS TS tow weuliwmwe

-40V

OUTPUT ) | MS/CM Cl INPUT WAVEFORM R5 36K 22 UUF +150V a Per ane eee cae +110V R2 R6 Le 11K 360K ~~, r nn nN +90V 1MS/CM 0) e O -I5V -30V -150V -1§0V OUTPUT WAVEFORM